1. Field of the Invention
The disclosure relates in general to a three-dimensional (3D) stacked semiconductor structure and method of manufacturing the same, and more particularly to the 3D stacked semiconductor structure in a fan-out region of a 3D flash memory and method of manufacturing the same.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed.
With the development of size reduction of device, the distance between gates in the array region of the three-dimensional (3D) stacked flash memory structure is reduced consequently. Take a 3D NAND-type flash memory structure as an example. Without ion implant, the junctions between the gates still occur after voltage applies to the structure (so called as a 3D stacked junction-free NAND structure). FIG. 1 is a perspective view of part of a 3D stacked NAND flash memory. The 3D stacked NAND flash memory includes an array region 11 and a fan-out region 13. The 3D stacked semiconductor structure in the fan-out region 13 comprises a stack of several oxide layers 131 and polysilicon layers 133 (as gate material) arranged alternately. The contact holes 135 is formed vertically to the stack and filled with conductors for connecting each of the conductive layers to outer circuits. However, the resistances of the polysilicon layers 133 in the fan-out region 13 have to be decreased by ion implanting. High resistances of the polysilicon layers 133 would have considerable effect on the programming speed (e.g. read latency) of the 3D stacked flash memory, such as causing response delay or even out of operation. Currently, the polysilicon layers 133 in the fan-out region 13 are ion implanted layer by layer, which is time-consuming and expansive.